This is a first-year graduate-level, three-credit-hour course that combines lecture and laboratory components. The goal of this course is to provide students with the opportunity to learn and practice the most common design steps in the VLSI chip design and manufacturing flow. Topics include a review of combinational and sequential logic design, logic minimization, full-custom transistor-level and gate-level implementation of digital circuits, and design using Verilog HDL. All design activities will be carried out using Cadence or Synopsys toolsets.
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